DISISSCH1=DISISSCH1_0, FPEXCODIS=FPEXCODIS_0, DISFPUISSOPT=DISFPUISSOPT_0, DISDI=DISDI_0, DISCRITAXIRUR=DISCRITAXIRUR_0, DISBTACREAD=DISBTACREAD_0, DISDYNADD=DISDYNADD_0, DISBTACALLOC=DISBTACALLOC_0, DISFOLD=DISFOLD_0, DISRAMODE=DISRAMODE_0, DISCRITAXIRUW=DISCRITAXIRUW_0
Auxiliary Control Register,
| DISFOLD | Disables folding of IT instructions. 0 (DISFOLD_0): Normal operation. |
| FPEXCODIS | Disables FPU exception outputs. 0 (FPEXCODIS_0): Normal operation. 1 (FPEXCODIS_1): FPU exception outputs are disabled. |
| DISRAMODE | Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions. 0 (DISRAMODE_0): Normal operation. 1 (DISRAMODE_1): Dynamic disabled. |
| DISITMATBFLUSH | Disables ITM and DWT ATB flush. 1 (DISITMATBFLUSH_1): ITM and DWT ATB flush disabled, this bit is always 1. |
| DISBTACREAD | Disables BTAC read. 0 (DISBTACREAD_0): Normal operation. 1 (DISBTACREAD_1): BTAC is not used and only static branch prediction can occur. |
| DISBTACALLOC | Disables BTAC allocate. 0 (DISBTACALLOC_0): Normal operation. 1 (DISBTACALLOC_1): No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated. |
| DISCRITAXIRUR | Disables critical AXI Read-Under-Read. 0 (DISCRITAXIRUR_0): Normal operation. 1 (DISCRITAXIRUR_1): An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set. |
| DISDI | Disables dual-issued. 0 (DISDI_0): Normal operation. 1 (DISDI_1): Nothing can be dual-issued when this instruction type is in channel 0. |
| DISISSCH1 | Disables dual-issued. 0 (DISISSCH1_0): Normal operation. 1 (DISISSCH1_1): Nothing can be dual-issued when this instruction type is in channel 1. |
| DISDYNADD | Disables dynamic allocation of ADD and SUB instructions 0 (DISDYNADD_0): Normal operation. Some ADD and SUB instrctions are resolved in EX1. 1 (DISDYNADD_1): All ADD and SUB instructions are resolved in EX2. |
| DISCRITAXIRUW | Disables critical AXI read-under-write 0 (DISCRITAXIRUW_0): Normal operation. This is backwards compatible with r0. 1 (DISCRITAXIRUW_1): AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete. |
| DISFPUISSOPT | Disables critical AXI read-under-write 0 (DISFPUISSOPT_0): Normal operation. |